The present invention relates to a method for manufacturing a thin film structure on a flattened upper surface, in particular, to a method for manufacturing a thin film structure on a flattened upper surface while forming patterns on two layers of thin films respectively by using a single mask, which is in the filed of microelectronics manufacture. The present invention also relates to a method for manufacturing a fringe field switching type liquid crystal display array substrate.
Thin film process is widely used in manufacturing of microelectronics. The thin film process typically comprises the steps of: depositing various thin films such as metal layers, insulating layers and semiconductor layers on an underlying structure, and patterning by a photolithography process to provide circuits functions. The photolithography process is a method in which a photosensitive layer (photoresist) is formed on the thin film and is subjected to exposing and developing process using a pre-designed mask and then the portion of the thin film that is not covered by the photosensitive layer is etched off so as to pattern the thin film.
In the thin film process, since the patterns to be formed in respective layers are different, it is inevitable that some line segments of respective patterns such as gate lines and data lines of an array substrate of a liquid crystal display will be overlapped. Since the thin film previously deposited on a flat underlying structure is patterned, it will protrude from the underlying structure to a certain height. Therefore when other thin films are sequentially deposited on the top of each other, a step difference will be increasingly introduced in the overlying thin film, even though the individual height might be very small. Such step difference might cause patterns breakage in some layers at overlapped positions, which in turn leads to not only circuit disconnection in those layers, but also undesirable connection of layers originally insulated from each other so as to form short circuit.
Next, an existing method for manufacturing a fringe field switching type liquid crystal display array substrate will be illustrated as an example to explain the formation of a step difference.
Please refer to FIGS. 1A-1E, in which FIG. 1A is a cross sectional view after the first photolithography process during the manufacturing of a fringe field switching type liquid crystal display array substrate of the prior art; FIG. 1B is a cross sectional view after the second photolithography process during the manufacturing of a fringe field switching type liquid crystal display array substrate of the prior art; FIG. 1C is a cross sectional view after the third photolithography process during the manufacturing of a fringe field switching type liquid crystal display array substrate of the prior art; FIG. 1D is a cross sectional view after the fourth photolithography process during the manufacturing of a fringe field switching type liquid crystal display array substrate of the prior art; and FIG. 1E is a cross sectional view after the fifth photolithography process during the manufacturing of a fringe field switching type liquid crystal display array substrate of the prior art. The manufacturing steps are as follows.
First, a substrate 10 is provided, and a metal layer is deposited and subjected to the first photolithography process to form a common electrode 11 on the substrate 10, as shown in FIG. 1A. A metal layer is deposited subsequently on the substrate 10 and is subjected to the second photolithography process to form a gate line and a gate electrode 12 that is integrated with the gate line, as shown in FIG. 1B. Then, a gate insulating layer 13 is deposited on the substrate 10 and covers the gate line, the gate electrode 12 and the common electrode 11. Then, a semiconductor layer 14 and a doped semiconductor layer 15 as well as a source and drain metal layer are deposited subsequently, and are subjected to the third photolithography process to form TFT channel, source electrode 16 and drain electrode 17 by using a dual-tone mask, as shown in FIG. 1C. Next, a passivation layer 18 is deposited to cover the entire substrate 10 and is subjected to the fourth photolithography process to form vias 181, as shown in FIG. 1D. Finally, a transparent conductive material is deposited and is subjected to the fifth photolithography process to form a pixel electrode 19, as shown in FIG. 1E.
As shown in FIGS. 1A-1E, in a structure obtained by the above method, since the gate electrode 12 and the common electrode 11 protrude from the substrate, a step difference will be introduced in the thin films overlying the gate electrode and the common electrode, causing defects such as disconnection and short circuit.
Furthermore, since the mask used in the thin film process is expensive, how to reduce the number of masks to be used, in particular, how to form patterns in multiple thin film layers by using a single mask has become a key issue for cost reduction and enhancement of competitiveness in the semiconductor industry. In the prior art, a dual-tone mask is typically adopted to substitute two ordinary masks for the purpose of reducing the number of masks to be used. So-called dual-tone mask is a gray-tone mask or half-tone mask. The gray-tone mask is a mask formed with a grating pattern. The half-tone mask is a mask having difference thicknesses.
However, there is no technical solution disclosed in the prior art in which patterns are formed in multiple thin film layers by using a single mask while an upper surface of the multiple layers of thin films is flattened so that it is possible to prevent disconnection and short circuit from occurring, but also to reduce the number of masks to be used.